Aeneon XTune DDR3-1333 2 GB
Memory Kit Review
With DDR3 rapidly expanding into the market, we are seeing more and
more manufacturers jumping into the fray. Today we will be
looking at the Aeneon XTune 2GB DDR3-1333 kit. Aeneon may not
be a name most of us are familiar with, but the company behind the
new Aeneon Brand is Qimonda; one if the leading providers of OEM
memory products world wide. With that kind of backing and one
of the lowest prices we have seen yet, how does the XTune DDR3 stack
up? Let's find out!
- 2 x 1GB (2GB KIT) Memory Modules
- Speed grade DDR3-1333 CL8 at 1.5V
- Provides up to 10664 Megabytes per second on
- 240-Pin Dual Inline Memory Module (DIMM)
with gold contacts
- Highest quality heat spreader to keep the
- Fitting in industry standard motherboards
The 1 GB single module can be organized as
- 128M x 64-bit DDR3-1333 per channel, based on 16
x 512Mb DDR3 FBGA components.
The single module is tested to run at DDR3-1333
at a latency timing of 8-8-8-15 at the standard DDR3 voltage value
of 1.5 V.
The Dual Channel Kit is coming with two identical
modules tested together in DUAL CHANNEL MODE at DDR3-1333 at a
latency timing of 8-8-8-15 on several platforms.
To use DDR3, your system motherboard must have
240-pin DIMM slots and a chipset that supports DDR3 — which is a
different technology than that of than its predecessors, DDR2 and
DDR. DDR3 incorporates different sockets; they are not
interchangeable or backward-compatible.
To quote Wikipedia:
"DDR3 memory comes with
a promise of a power consumption reduction of 30% compared to
current commercial DDR2 modules due to DDR3's 1.5 V supply voltage,
compared to DDR2's 1.8 V or DDR's 2.5 V. This supply voltage works
well with the 90 nm fabrication technology used for most DDR3 chips.
Some manufacturers further propose to use "dual-gate" transistors to
reduce leakage of current.
"The main benefit of
DDR3 comes from the higher bandwidth made possible by DDR3's 8 bit
deep prefetch buffer, whereas DDR2's is 4 bits, and DDR's is 2 bits
modules could transfer data at the effective clock rate of 800–1600
MHz (using both edges of a 400–800 MHz I/O clock), compared to
DDR2's current range of effective 400–800 MHz (200–400 MHz clock) or
DDR's range of 200–400 MHz (100–200 MHz). To date, such bandwidth
requirements have been mainly found in the graphics market, where
fast transfer of information between framebuffers